It is known in the art of digital circuitry to perform integration by using a delay element and an adder circuit. The signal to be integrated is applied to one input (addend) of the adder circuit. The output of the adder circuit is coupled to the input of the delay element, the output of which is coupled to the second input (augend) of the adder circuit. The integrated signal may be taken from either the output of the adder circuit or the output of the delay element. See for example the article by H. Urkowitz, "Analysis and Synthesis of Delay Line Periodic Filters," IRE Trans. on Circuitry Theory, June 1957, pp 41-53.
Frequently it is desired to both scale and truncate the values provided by the integrator. Truncation is performed in order to reduce the number of sample bits processed, in order to reduce the size of the processing circuitry or minimize the processing time. It has been found that undesirable effects may occur if the truncation is performed in the integrator loop, that is, between the delay element and the adder. These effects are manifested as inaccuracies in the processed signals, undesirable excess signal build up for certain signals and possible oscillations or limit cycles. It is an object of the present invention to provide a bit-serial integrator circuit which provides both scaling and truncation; provides integration with full bit accuracy, and requires a minimum of hardware.